Tilera startup by fables semiconductor, started its initial and primary efforts to rebuild and rework on RISC revolution with more than 65-core processor that have the capacity of putting an extraordinary amount of hardware in the hands of complier. It has been done before any cloud computing become an exhortation and quadcore assume the power of being mainstream in the market. The original and unique Tile64 is standing on MIT’s RAW project and development. The basic idea and main purpose behind the project was to utilize a grid of light weighted cores and an on-chip mesh network to increase CUP performance. As sometimes wires delay from tripping between cores and results in being exposed to a complier for programming purposes.

This is the fact that nobody has ever seen a pair of third party benchmarks for CPU of Tilera, as nobody can say anything to the company about its success because of the boosting seen in CUP performance. It seems that it has realized sometime important and started repackaging now many-core+ mesh ideas in the form of performance for the cloud datacenters. In running the race of cloud push, Quanta and Tilera are competing to announce a new cloud server known as the S2Q having the capacity of packing around 512 cores inside two rack units. However, this is regarded less power or space in comparison to 512-core SeaMicro server which was publicized last week; still both of them are not comparable in spite of the target market and the same core count.

Very simple VLIW design having a load store pipe and two integers ALUs is implemented by Tilera’s cores. Each core possesses L2 cache and a small bit of L1 associated with it. And it is also connected and joined to a chip-wide and the larger mesh network, fully articulate L3 cache through a private and small switch. The short of vector hardware and floating point are not able to harm Tilera on cloud workloads. But, due to the differences between 512 cores of the Atom and 512 cores of Tilera are quite deeper in comparison to lack of support necessary for 2 arithmetic types.

Tilera has been promoting its Tilepro-64 in the form of 64 cores having the value of general purpose compute power. Its signal feature also indicates that cores have been built to be teamed up jointly to solve problems. This is clear that VLIW nature of cores place 100% burden onto the complier for greatest performance and complier is able to know the latency between different cores. It means that Tilera CPU is able to do a type of reverse SMT theoretically, where at least two or more cores are in the condition of executing instructions sent from a single thread. It simply means that complier is completely able to execute some type of instructions related to pipelining all over the cores. Moreover, more than a single core is able to do the same thing which a single Atom core is able to do.